How to flash S32G399 M7 Core to boot from QSPI or any flash memory using Lauterbach

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How to flash S32G399 M7 Core to boot from QSPI or any flash memory using Lauterbach

3,924 Views
rishabh-j-dev
Contributor I

Hi, I have a S32G-VNP-RDB2 kit. I am trying to run a sample program for the M7 core to put data out of FlexCan0, which works when flashed to ram using Lauterbach with the script attached in the description. Now I am trying flash the elf file to non volatile memory but I am not successful in doing that yet. I changed the &load_to variable to flash as mentioned in the run.cmm script but haven't been successful for the M7 to boot from the flash. Any leads would be helpful thanks.

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

When you are saying:

"I am trying flash the elf file to non volatile memory but I am not successful in doing that yet"

Are you flashing the whole blob image with the IVT structure? Or just the plain binary/elf? If so, S32G boot sequence might be different from other processors. It requires the creation of an IVT for it to boot from external memory. The creation of this structure is explained under the "Software Enablement Guide" available under the RDB2 product page (link: S32G2 Vehicle Networking Reference Design | NXP Semiconductors).

On regards of your debugger, we are not seeing any information for Lauterbach Flash programming at this moment, we do apologize. What we seem to find are the steps for S32 Debug Probe:

HOWTO: JTAG Flash Programming with S32 Debugger an... - NXP Community

There is also the possibility of flashing the external flash with the UART0 interface, could be useful.

Please, let us know.

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rishabh-j-dev
Contributor I
I am trying to flash the plain elf file generated by the S32 design compile and ide for the cortex M7. Let me try to create an IVT out of this elf. Just to confirm if I flash this IVT blob image to QSPI the default settings of the RCON pins RCON0 RCON1 and RCON2 are all low (000) which should enable to boot from QSPI and the Bootmode[0] =1 Bootmode[1] = 0 which enables to boot from RCON configuration.
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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

The IVT will need the raw binary of your application, this is explained under the Software Enablement Guide. Still, let us know if you require more information on this regard.

The configuration for QSPI boot under RDB2 is shared under the RDB2 User Guide:

DanielAguirre_0-1698269232762.png

This User Guide is available under the RDB2 product page (link: S32G2 Vehicle Networking Reference Design | NXP Semiconductors). But in summary, you are correct, all RCON values should be 0 and BOOTMOD value should be BOOTMOD[0] = 1 and BOOTMOD[1] = 0.

Please, let us know.

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rishabh-j-dev
Contributor I

Hi Daniel, I followed your advice and went through the documentation -Flashing Binaries to S32G-VNP-RDB3 Board and SOFTWARE ENABLEMENT GUIDE. I used the FreeRtos example for S32G3xx project which blinks led. I flashed this porject using Lauterbach to sram and led blinks as expected. Now my goal is to flash this in the nor flash so I create IVT bin file as mentioned enablement guide and flash the QSPI serially via uart0 successfully as attached in the screenshot. Also made sure the SW4 7th switch is off and SW10 1st switch ON and the 2nd off, also SW9 all off. Then I power cycle expecting to boot from qspi flash but I don't see the led blink which say's that it hasn't boot from the QSPI.

Attached Screenshots of the IVT configuration, the successful flash and the IVT mage blob

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

For the images you have provided, we found some problems with your IVT configuration.

DanielAguirre_0-1698429901081.png

The first problem is related to the QSPI parameters field. It seems you have enabled the QSPI parameters configuration but you are not sending any configuration in it. You can either send a configuration by selecting one from the following path:

"C:\nxp\S32DS.3.5\eclipse\mcu_data\processors\S32G399A\PlatformSDK_S32XX_2022_07\quadspi\default_boot_images"

This path can vary depending on the versions of the processor/IDE/RTD.

If you are following the SW Enablement Guide and modified the linker as per the guide, the QSPI parameters might not be required, since the size of the binary is smaller.

The second problem is related to the selection of the external NOR Flash, the one you are selecting is not embedded inside the RDB3, the one being used is the "MX25UM51245G/MX25UW51245G".

Also, we recommend looking into creating the IVT with a non-FreeRTOS example of blink ("Siul2_Dio_ToggleLed_S32G399A_M7"), for the simplicity.

Please, let us know.

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rishabh-j-dev
Contributor I

Hello So as per your suggestion I tried your suggestion I tried "Siul2_Dio_ToggleLed_S32G399A_M7"

and compiled it, unfortunately doesn't compile right, I removed the nano spec flag in the compile properties as well but still not successful.

Building file: ../generate/src/OsIf_Cfg.c

make: *** [src/subdir.mk:20: src/main.o] Error 1

make: *** Waiting for unfinished jobs....

arm-none-eabi-gcc.exe: fatal error: cannot read spec file 'nano.specs': No such file or directory

compilation terminated.

make: *** [generate/src/subdir.mk:25: generate/src/Clock_Ip_BOARD_InitPeripherals_PBcfg.o] Error 1

Invoking: Standard S32DS C Compiler

arm-none-eabi-gcc "@generate/src/Clock_Ip_BOARD_InitPeripherals_PBcfg.args" -MMD -MP -MF"generate/src/OsIf_Cfg.d" -MT"generate/src/OsIf_Cfg.o" -o "generate/src/OsIf_Cfg.o" "../generate/src/OsIf_Cfg.c"

arm-none-eabi-gcc.exe: fatal error: cannot read spec file 'nano.specs': No such file or directory

compilation terminated.

make: *** [generate/src/subdir.mk:26: generate/src/Clock_Ip_Cfg.o] Error 1

arm-none-eabi-gcc.exe: fatal error: cannot read spec file 'nano.specs': No such file or directory

compilation terminated.

make: *** [generate/src/subdir.mk:26: generate/src/OsIf_Cfg.o] Error 1

"make -j16 all" terminated with exit code 2. Build might be incomplete.

 

10:47:27 Build Failed. 5 errors, 0 warnings. (took 475ms)

 

Now going back to the FreeRtos example I followed your suggestion and changed the algorithm to MX25UM51245G and QSPI parameter is disabled.Still not successful to boot from the QSPI, I have attached the linker screenshot, Successful flash picture and the init vector table and the RCON and SW9 and SW10 switch configuration

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Seems odd, that your compilation is failing, since the example works out-of-the-box, once the code is generated from Config Tools.

As for your IVT, it seems that you are modifying the linker of the example, since we can see that the default linker is as follows:

DanielAguirre_0-1698791458162.png

Also, the linker does not seem to follow the SW Enablement Guide. Can you confirm that following the linker used under the SW enablement guide provides the same result?

There is a default MPU configuration being loaded to each example, if the MPU is not modified. You could also try and disable the MPU to understand if this is related to it.

Please, let us know.

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rishabh-j-dev
Contributor I

Attaching attachment with screenshots of the isr, linker file and the successful flashing of the QSPI

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Thanks for your feedback. We seem to see that you are using the default linker of the example, not the SW Enablement Guide modified linker. If you are using the default linker, you are required to load a QSPI reconfiguration parameters binary, since the image is too big and the deafult QSPI speed is not enough to comply with the following S32G requirement [Page 1347, S32G2 Reference Manual, Rev. 7, February 2023]:

"BootROM sets a timeout of 500ms when downloading the application image. User must ensure that the maximum image size can be downloaded within this time. The image size would depend on the configuration used."

If you are looking for the QSPI reconfiguration parameters binary, you should see them available under the following path:

"C:\nxp\S32DS.3.4\eclipse\mcu_data\processors\S32G274A_Rev2\PlatformSDK_S32XX_2022_03\quadspi\default_boot_images"

Where it can vary depending on which IDE/RTD version you have installed.

Also, the example does not configure clocks. When you load it from QSPI, you will see that the LED toggles slower than when using a debugger. This, as said before, is due to the clocks not being configured.

Please, let us know.

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3,678 Views
rishabh-j-dev
Contributor I

Thanks a ton Daniel ! It worked as you mentioned the led toggles really slow. Is there an example of how to configure the clock for QSPI ? If I use emmc would I still need to configure clock ?

 

Also it would be really helpful to know the actual reason why the led toggles slow, like I assume the bootrom loads the code from QSPI to sram to execute how does the clock come into picture here ?

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

We may not have explained correctly the situation. This is due to selecting an external interface to boot, not using the debugger. As for how to initialize the clocks, the SW enablement guide provides under Page 16 some steps to add the clock initialization to the code. You can also reuse the clock initialization from a different example (like UART).

The explanation is that the BootROM requires to configure the clocks in a certain way so that it can complete its objective. If no reconfiguration is done, then the clocks will remain how the BootROM configured them.

Please, let us know.

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3,544 Views
rishabh-j-dev
Contributor I

Hi Daniel, I used the clock example provided in the uart example but it's not able to boot. What do you think might be missing here. Attached is the project workspace.

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Which example of UART did you use?

We copy the following code and see the LED blinking at the expected speed:

DanielAguirre_0-1699549354769.png

DanielAguirre_1-1699549377661.png

This was copied from the "Linflexd_Uart_Ip_Example_S32G274A_M7", since it is the non-AUTOSAR example.

Please, let us know.

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3,731 Views
rishabh-j-dev
Contributor I

Hello I got Siul2_Dio_ToggleLed_S32G399A_M7 default project (no changes ) compiling and used Lauterbach and checked the RGB led blinks so that is good. Now I follow the steps mentioned in the application node to create the blob and flash QSPI via the uart. Turn the power off, have all RCON bits low and the SW10 1st switch ON and the 2nd off, also SW9 all off. Turned it back on the RGB led doesn't toggle. Attached are  the binary executable and blobs

 

I have attached 4 attachment here. Siul2_Dio_ToggleLed_S32G399A_M7.bin is the bin file generated on building. Siul2_Dio_ToggleLed_S32G399A_M7_bl.bin is the exported bin file from Step 9 of LIGHT UP RGB LED: MAKE IMAGE BY IVT TOOL. Siul2_Dio_ToggleLed_S32G399A_M7_blob.bin is the final blob bin. Also attached the setup picture here

 

I am creating a separate reply for other attachment as I can only attach 5 in this reply

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rishabh-j-dev
Contributor I

Also attaching the zipped folder of the project

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3,788 Views
rishabh-j-dev
Contributor I

Thank you let me give it a try

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