Amarile’s Post

Wouldn’t it be nice if you could install an FPGA tool chain from PyPI? While this sounds too outlandish to be possible, through the magic of open-source, it is a reality today. YoWASP is an open-source project of the FOSSi Foundation. It was created to make it easier to install software for the Glasgow Interface Explorer, which utilizes the open-source FPGA tool chain from YosysHQ. To simplify installation across platforms, they ported the tool chain to WebAssembly. This has some performance limitations, but not as significant as you might expect. You can still install the tools natively for full performance, but now there is another option to make FPGA development and tools like Glasgow even more accessible. #opensource #pypi #yosys #yowasp #webassembly

Might be interesting for those looking forward to developing low cost safety-critical products.

In case you missed it, you can now view the recording of Dr. Steffen Lindner’s recent P4 Developer Days talk on the P4TG traffic generator and analyzer | https://bit.ly/4aTbRrH “We present P4TG, an open-source P4-based traffic generator (TG) which runs on the programmable Intel Tofino ASIC. In generation mode, P4TG is capable of generating traffic up to 1 Tb/s split across 10x 100 Gb/s ports. Thereby it measures rates directly in the data plane. Generated traffic may be fed back from the output to the input ports, possibly through other equipment, to record packet loss, packet reordering, inter-arrival times (IATs) and sampled round trip times (RTTs). Further, it supports VLAN, QinQ, and MPLS encapsulation. In analysis mode, P4TG measures rates on the input ports and IATs, and forwards traffic through its output ports. Existing software or P4-based traffic generators either lack the required accuracy, do not support high data rates, or do not provide sufficiently integrated measurement capabilities.” #p4 #programminglanguage #opensource

Exciting news! The Flexible Safety RTOS is now seamlessly integrated into the netX90 SoC system development environment. As we all know, developing applications on the netX90 device can be quite challenging. That's why I'm thrilled to share this game-changing integration that simplifies the entire development process. With the integration of the Flexible Safety RTOS, developers can now enjoy a wide range of benefits that enhance both productivity and product quality. In addition to traditional RTOS services like tasks, queues, and semaphores, this powerful solution also offers memory protection and integrated self-tests. Memory protection ensures that critical data stays secure, while integrated self-tests help identify any potential issues early in the development cycle. By leveraging these features, developers can significantly reduce time to market for their applications using any of the Hilscher supported field bus protocols. But it doesn't end there! This integration empowers you to confidently tackle complex projects by providing a solid foundation for your application development journey. From minimizing errors to streamlining processes, it enables you to focus on what truly matters – delivering exceptional solutions to your clients. So here's my call to action: explore the possibilities this integration brings and take advantage of its remarkable capabilities. Don't let development hurdles slow you down anymore – contact us and simplify your application development with the netX90 SoC system development environment powered by the Flexible Safety RTOS. #netX90Development #ApplicationSimplification #FlexibleSafetyRTOS

🚀 #Day 6 of the #100rtldays challenge: Implementation of the circuit! 🧠 Today i have instantiated 2 verilog module within the other one to complete the circuit. Module A takes inputs x and y and produces output z using the assignment z = (x ^ y) & x. This module leverages bitwise XOR and AND operations to achieve its functionality. Module B, on the other hand, also takes inputs x and y and outputs z, calculated as z = ~(x ^ y). Here, we use bitwise XOR and NOT operations to achieve the desired result. Module CH6 combines the outputs of A and B. It instantiates two instances of both A and B and utilizes logic gates to perform logical OR and AND operations on their outputs. Finally, it calculates the output z as the XOR of the results from these logic operations. 🌟 #RTLDesign #DigitalLogic #HardwareDesign #100DaysOfRTL #100rtldayschallenge #ieeecasskerala #ieeecasssahrday

Objectives Task 1: Create the Contoso resource group. Task 2: Create the CoreServicesVnet virtual network and subnets. Task 3: Create the ManufacturingVnet virtual network and subnets. Task 4: Create the ResearchVnet virtual network and subnets. Task 5: Verify the creation of the virtual networks and subnets.

Rugged, all-weather #KRYPTON DAQ modules allow you to put the A/D right next to the measuring point. Single or multi-channel modules are easily interconnected via a single EtherCAT cable. Compatible with all major sensors. Includes the best DAQ software in the world, DewesoftX. NO software license fees, and free updates for life!  https://lnkd.in/eeeNpk65  #WeAreDewesoft #DAQ #testing #measurement #EtherCAT

This video is about #oemfactory #Olycom production of type 4 #poeswitch It offers poe status monitoring, poe budget programming and enabling/disabling poe functions. #industrialmanufacturing #ethernetswitch https://lnkd.in/gpKZcQUm